With development of panel display, high resolution and narrow border become trends of development, and integrating a gate drive circuit on a display panel is the most important solution to achieve high resolution and narrow border.
FIG. 1 shows a circuit diagram of a basic shift register cell used for a gate drive circuit in the prior art. As shown in FIG. 1, the basic shift register cell comprises a pull-up transistor T100, an output pull-down transistor T200, a bootstrap capacitor C1, a pull-up control transistor T300, a pull-down control transistor T400, a pull-down unit 13, a first clock signal input terminal CLK, a drive signal input terminal OUT(n−1) and a drive signal output terminal OUT(n).
In FIG. 1, a pull-up node PU is a node connected with a gate of the pull-up transistor T100, a pull-down node PD is a node connected with a gate of the output pull-down transistor T200, and a start signal STV is inputted from the drive signal input terminal OUT(n−1).
FIG. 2 shows a timing diagram of signals during operation of the shift register cell in FIG. 1, wherein VGL represents a low level, and VGH represents a high level.
As shown in FIG. 2, when enhanced thin film transistors (TFTs) are used for implementing the basic shift register cell shown in FIG. 1, the basic shift register cell may operate normally (as indicated by solid line in FIG. 2), wherein the enhanced TFTs may be thin film transistors made of amorphous silicon (a-Si) or polycrystalline silicon (p-Si).
However, when depletion type TFTs are used for implementing the basic shift register cell shown in FIG. 1, as a threshold voltage of a depletion type TFT is less than zero (0), the basic shift register cell may not operate normally (as indicated by dash line in FIG. 2).
FIG. 3 and FIG. 4 show difference between an enhanced thin film transistor and a depletion type thin film transistor. Specifically, FIG. 3 shows a characteristic graph of an enhanced thin film transistor, wherein a vertical axis represents a drain current (iD) of the thin film transistor, and a lateral axis represents a gate-source voltage (VGS). It can be seen from FIG. 3, when VGS is 0, iD is 0, that is, with respect to an enhanced thin film transistor, when VGS is 0, the enhanced thin film transistor is turned off completely. FIG. 4 shows a characteristic graph of a depletion type thin film transistor, wherein a vertical axis represents a drain current (iD), and a lateral axis represents a gate-source voltage (VGS). However, It can be seen from FIG. 4, when VGS is 0, iD is far larger than 0, and only when VGS is a certain negative voltage, iD is 0.
However, in recent years, more and more attentions have been given to oxide thin film transistors with characteristic of depletion, which are considered as a semiconductor technology with great potential. Compared with a p-Si thin film transistor, fabrication process of an oxide thin film transistor is simpler, and cost of the oxide thin film transistor is lower. Compared with an a-Si thin film transistor, mobility of an oxide thin film transistor is higher. Thus, in future, oxide thin film transistors may very likely to be used as a mainstream backplane drive technique for various display panels (in particular, organic light emitting diode (OLED) and flexible display panels).
Therefore, there is a need to provide a shift register cell which may be implemented by depletion type TFTs.